An ASIC Architecture for Generating Optimum Mixed Polarity Reed-Muller Expression

Abstract: Logic function realization using Reed-Muller (RM) expression has manifold advantages over realization using SOP expression. In this paper, we present an ASIC architecture for generating optimum 3-variable mixed polarity RM expression. The ASIC based minimization is much faster than the software based minimization. The design is modeled using Verilog HDL and synthesized using Quartus II 4.2 software for Stratix EP1S10F484C5 FPGA device.